The present invention relates to timing circuits and, more particularly, to a delay-locked loop (DLL) circuit having a phase frequency detector.
FIG. 1 is a simplified block diagram of a conventional DLL 100. The DLL 100 may be used, for example, in a clock recovery system, an on-chip clock distribution system, or in a clock generator. The DLL 100 comprises a phase frequency (PF) detector 101, a charge pump 102, a capacitor AH, and a voltage-controlled delay (VCD) line 103.
The DLL 100 is expected to generate an output clock CLKOUT that has the same frequency as an input clock CLKIN and that is delayed by the VCD line 103 by exactly one period T of the input clock CLKIN. An initial delay τi introduced by the VCD line depends on various initial conditions, including the initial charge on the capacitor AH after power up. The DLL 100 is adapted to correct an initial delay τi that is within the range of T/2<τi<3Y/2 so that, after several cycles, the actual delay τ applied by the VCD line 103 equals the period T.
As explained in further detail below, the PF detector 101 controls the phase delay generated by the VCD line 103 based on a comparison of the input clock CLKIN to the output clock CLKOUT, which is fed back to the PF detector 101 from the VCD line 103. Based on the detected phase difference between the input clock CLKIN and the output clock CLKOUT, the PF detector 101 raises or lowers—using corresponding control signals UP and DOWN—a current output by the charge pump 102 to a node 102a. The node 102a corresponds to a first terminal of the capacitor AH. The second terminal of the capacitor AH is connected to a common ground node. Note that the capacitor AH acts as a low-pass filter for the DLL 100. The control voltage VCTRL at the node 102a rises or falls depending on the current provided by the charge pump 102 to the node 102a. 
The control signal UP is used to raise the control voltage VCTRL. The control signal DOWN is used to lower the control voltage VCTRL. When the UP signal is high and the DOWN signal is low, the capacitor AH charges and the control voltage VCTRL increases. When the UP control signal is low and the DOWN control signal is high, the capacitor AH discharges and the control voltage VCTRL decreases. When both UP signal and DOWN signal are high, the charge on capacitor AH is held steady. When both the UP signal and the DOWN signal are low, the charge on capacitor AH is similarly held steady.
The VCD line 103 comprises a plurality of buffers (not shown) connected in a serial chain, where the input to the first buffer is the input clock CLKIN and the output of the last buffer is the output clock CLKOUT. The delay introduced by each buffer is controlled by the control voltage VCTRL, which is provided to each buffer. Specifically, increasing the control voltage VCTRL decreases the delay, and decreasing the control voltage VCTRL increases the delay. The cumulative delay of all of the buffers of the VCD line 103 is the actual delay T.
The PF detector 101 comprises two D flip-flops 105 and 106 and an AND gate 104. The D input of each of the flip-flops 105 and 106 is connected to a supply voltage VDD. The reset input of each of the flip-flops 105 and 106 is connected to the output 104a of the AND gate 104. The clock inputs of the flip-flops 105 and 106 are connected, respectively, to the input clock CLKIN and the output clock CLKOUT. The Q outputs of the flip-flops 105 and 106 are, respectively, the UP signal on a node 101a and DOWN signal on a node 101b, which are also the inputs to the AND gate 104.
When a rising edge of the input clock CLKIN is received by the clock input of the flip-flop 105, the flip-flop 105 propagates the high (VDD) value at its D input, and the UP signal output via its Q output goes high. When a rising edge of the output clock CLKOUT is received by the clock input of the flip-flop 106, the flip-flop 106 propagates the high value (VDD) at its D input, and the DOWN signal output via its Q output goes high. When both the UP and DOWN signals are high, then the output 104a of the AND gate 104 goes high and resets both flip-flops 105 and 106, and both the UP and DOWN signals go low. Note that the operation of the PF detector 101 may be controlled by a PFD power-up control (not shown) to either provide power for normal operation of the PF detector 101 or cut off power to hold the signals of the PF detector 101 low.
FIG. 2 is an exemplary timing diagram 200 for the DLL 100 of FIG. 1 for an exemplary initial delay τi that is too short. Note that the black circles on the wave forms in FIG. 2 indicate exemplary corresponding upticks of the input clock CLKIN and the output clock CLKOUT. At time to, the input clock CLKIN goes high. At time t1, the PF detector 101 is powered up. At time t2, the output clock CLKOUT goes high, and the DOWN signal follows substantially simultaneously. At time t3, the input clock CLKIN goes high, and the UP signal follows substantially simultaneously. After a short delay, at time t4, the flip-flops 106 and 105 are reset, and the UP and DOWN signals go low.
The period T of the input clock CLKIN corresponds to the difference between times t3 and t0. The initial delay τi corresponds to the difference between times t2 and to. As can be seen, T/2<τi<T. While the DOWN signal is high and the UP signal is low—i.e., between times t2 and t3—the charge pump 102 lowers the control voltage VCTRL at the node 102a and, consequently, increases the delay introduced by the VCD line 103. Based on this initial delay τi and depending on a variety of other factors collectively referred to as the loop bandwidth of the DLL 100, it takes several cycles of the input clock CLKIN for the DLL 100 to achieve phase lock. At time t5, after phase lock has been achieved, the input clock CLKIN goes high. At time t6, after a delay τ of T, the output clock CLKOUT also goes high.
FIG. 3 is an exemplary timing diagram 300 for the DLL 100 of FIG. 1 for an exemplary initial delay τi that is too long. At time to, the input clock CLKIN goes high. At time t1, the PF detector 101 is powered up. At time t2, the input clock CLKIN goes high, and the UP signal follows substantially simultaneously. At time t3, the output clock CLKOUT goes high, and the DOWN signal follows substantially simultaneously. After a short delay, at time t4, the flip-flops 106 and 105 are reset, and the UP and DOWN signals go low.
The period T of the input clock CLKIN corresponds to the difference between times t2 and to. The initial delay τi corresponds to the difference between times t3 and to. As can be seen, T<τi<3T/2. While the UP signal is high and the DOWN signal is low—i.e., between times t2 and t3—the charge pump 102 raises the control voltage VCTRL at the node 102a and, consequently, reduces the delay introduced by the VCD line 103. Based on this initial delay τi and depending on the loop bandwidth of the DLL 100, it takes several cycles of the input clock CLKIN for the DLL 100 to achieve phase lock. At time t5, after phase lock has been achieved, the input clock CLKIN goes high. At time t6, after a delay τ of T, the output clock CLKOUT also goes high.
FIG. 4 is an exemplary timing diagram 400 for the DLL 100 of FIG. 1 for an exemplary initial delay τi that is excessively short. At time to, the input clock CLKIN goes high. At time t1, the output clock CLKOUT goes high. At time t2, the PF detector 101 is powered up. At time t3, the input clock CLKIN goes high, and the UP signal follows substantially simultaneously. At time t4, the output clock CLKOUT goes high, and the DOWN signal follows substantially simultaneously. After a short delay, at time t5, the flip-flops 106 and 105 are reset, and the UP and DOWN signals go low.
The period T of the input clock CLKIN corresponds to the difference between times t3 and to. The initial delay τi corresponds to the difference between times t1 and t0. As can be seen, τi<T/2. While the UP signal is high and the DOWN signal is low, i.e., between times t3 and t4, the charge pump 102 raises the control voltage VCTRL at the node 102a and, consequently, reduces the delay introduced by the VCD line 103. Based on this initial delay τi and depending on the loop bandwidth of the DLL 100, it takes several cycles of the input clock CLKIN for the DLL 100 to achieve phase lock. Note, however, that this is an undesired false lock. At time t6, after false phase lock has occurred, the input clock CLKIN goes high, and, substantially simultaneously, the output clock CLKOUT follows.
FIG. 5 is an exemplary timing diagram 500 for the DLL 100 of FIG. 1 for an exemplary initial delay τi that is excessively long. At time to, the input clock CLKIN goes high. At time t1, the PF detector 101 is powered up. At time t2, the input clock CLKIN goes high again. At time t3, the output clock CLKOUT goes high, and the DOWN signal follows substantially simultaneously. At time t4, the input clock CLKIN goes high, and the UP signal follows substantially simultaneously. After a short delay, at time t5, the flip-flops 106 and 105 are reset, and the UP and DOWN signals go low.
The period T of the input clock CLKIN corresponds to the difference between times t2 and to. The initial delay τi corresponds to the difference between times t3 and to. As can be seen, 3T/2<τi. While the DOWN signal is high and the UP signal is low—i.e., between times t3 and t4—the charge pump 102 lowers the control voltage VCTRL at the node 102a and, consequently, increases the delay introduced by the VCD line 103. Based on this initial delay τi and depending on the loop bandwidth of the DLL 100, it takes several cycles of the input clock CLKIN for the DLL 100 to achieve phase lock. Note, however, that this is an undesired harmonic lock. At time t6, after harmonic phase lock has occurred, the input clock CLKIN goes high. At time t7, 2T later, the output clock CLKOUT follows.
Both false lock and harmonic lock are undesirable conditions for the DLL 100. False locking or harmonic locking are problematic if, for example, the circuit containing the DLL 100 relies on intermediate signals from the VCD line 103 to generate signals. Some prior-art solutions for harmonic lock include the addition of circuitry to detect a harmonic lock situation and provide an alert. Some other prior-art solutions include additional circuitry to prevent harmonic lock for initial delays of up to 2T. Other solutions may provide additional benefits.